Global Channel Read Write Resume Register
| RWR0 | XDMAC Channel 0 Read Write Resume Bit |
| RWR1 | XDMAC Channel 1 Read Write Resume Bit |
| RWR2 | XDMAC Channel 2 Read Write Resume Bit |
| RWR3 | XDMAC Channel 3 Read Write Resume Bit |
| RWR4 | XDMAC Channel 4 Read Write Resume Bit |
| RWR5 | XDMAC Channel 5 Read Write Resume Bit |
| RWR6 | XDMAC Channel 6 Read Write Resume Bit |
| RWR7 | XDMAC Channel 7 Read Write Resume Bit |
| RWR8 | XDMAC Channel 8 Read Write Resume Bit |
| RWR9 | XDMAC Channel 9 Read Write Resume Bit |
| RWR10 | XDMAC Channel 10 Read Write Resume Bit |
| RWR11 | XDMAC Channel 11 Read Write Resume Bit |
| RWR12 | XDMAC Channel 12 Read Write Resume Bit |
| RWR13 | XDMAC Channel 13 Read Write Resume Bit |
| RWR14 | XDMAC Channel 14 Read Write Resume Bit |
| RWR15 | XDMAC Channel 15 Read Write Resume Bit |
| RWR16 | XDMAC Channel 16 Read Write Resume Bit |
| RWR17 | XDMAC Channel 17 Read Write Resume Bit |
| RWR18 | XDMAC Channel 18 Read Write Resume Bit |
| RWR19 | XDMAC Channel 19 Read Write Resume Bit |
| RWR20 | XDMAC Channel 20 Read Write Resume Bit |
| RWR21 | XDMAC Channel 21 Read Write Resume Bit |
| RWR22 | XDMAC Channel 22 Read Write Resume Bit |
| RWR23 | XDMAC Channel 23 Read Write Resume Bit |